Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device

ABSTRACT

It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.

TECHNICAL FIELD

The present invention relates to a semiconductor device, a method ofgenerating a semiconductor device, a method of manufacturing asemiconductor device and an apparatus for generating a semiconductordevice, and more particularly to a semiconductor device including abypass capacitor and an inductor for a countermeasure against a noise ofthe semiconductor device, and a method of generating a pattern thereof.

BACKGROUND ART

As a matter of course, the utilization scope of an LSI in a computer hasbeen enlarged for communicating apparatuses such as a portabletelephone, general household appliances, toys and cars. On the otherhand, however, there are problems in that an electromagneticinterference (EMI) generated from these products causes the radiointerference of a receiver such as a television or a radio and themalfunction of other systems. A countermeasure in the whole productssuch as filtering or shielding has also been taken against theseproblems. In respect of an increase in the number of components, anincrease in a cost and the difficulty of a countermeasure in a product,the noise suppression of an LSI package has been greatly demanded.

In such a situation, the LSI of each product is placed as a key deviceand an increase in the scale and speed of the LSI has been demanded inorder to maintain the competitiveness of the product. In order to meetthese demands in a reduction in a product cycle, it is necessary toautomate an LSI design. There has been increased a necessity foremploying a synchronous design as the condition of the introduction of adesign automation technique under the existing circumstances. If allcircuits are operated synchronously with a reference clock and the LSIhas a large scale and a high speed, an instantaneous current is veryincreased. Consequently, an increase in the electromagnetic interferenceis caused.

With the microfabrication of the LSI and an increase in the speed of anoperating frequency, thus, countermeasures against latch up and a noisehave been great problems.

In a method of designing a cell base, generally, a diffusion region anda through hole are formed in a substrate cell as the countermeasureagainst latch up. Consequently, a contact is formed and a substrate or awell is fixed to have a supply potential through the contact.

If a substrate contact is added into the substrate cell as thecountermeasure against latch up, however, a chip area is increased.

The inventors have proposed a method of enhancing a latch up breakdownvoltage, reducing a noise radiation and reducing a malfunction caused bya noise entering from the outside while suppressing an increase in thearea of a semiconductor device by providing a substrate contact under apower wiring and arranging a capacitor having a cell bypassed betweenthe power wiring and a ground wiring in order to prevent an increase ina chip area (JP-A-2000-208634).

The method serves to automatically generate the pattern of asemiconductor device, comprising the steps of generating a layoutincluding a cell having an MIS structure on a semiconductor substrateand the pattern of a power wiring and a ground wiring, generating alayout including a cell having an MIS structure on the semiconductorsubstrate and the patterns of a power wiring and a ground wiring, andautomatically generating the pattern of a bypass capacitor having theMIS structure constituted by the semiconductor substrate, a capacitiveinsulating film and an electrode to overlap with the pattern of thepower wiring.

According to this method, the power wiring pattern has already beenformed before the formation of the bypass capacitor including adiffusion layer and a through hole. Therefore, the bypass capacitor canbe formed by utilizing the power wiring pattern so that a highintegrated semiconductor device can easily be formed.

As a specific example, FIG. 20 shows an example of the bypass capacitor,in which the bypass capacitor is formed between a polysilicon electrode(gate electrode) 71 and a substrate, and a capacitive insulating film (agate insulating film which is not shown) provided therebetween, and adiffusion region is formed to take the shape of a ring in a regioncorresponding to the outer periphery of a gate electrode, a virtualpower wiring pattern in a transverse direction and a virtual powerwiring pattern in a vertical direction are extracted in place of anoriginal power wiring pattern by using a kind of bypass capacitor arrayin which an electric potential on the substrate side is fetched andconnected in the diffusion region, and a bypass capacitor frame 70including them is formed. Moreover, a through hole 72 is formed on thesurface of the polysilicon electrode 71 in order to fetch an electricpotential on the polysilicon electrode side. Consequently, the patternof a semiconductor device provided with a bypass capacitor having thering-shaped polysilicon electrode 71 under a power wiring is generated.

According to this method, it is possible to reduce a power noise whichbecomes more serious with the microfabrication of a semiconductor deviceand an increase in the speed of an operating frequency. However, theeffect of reducing the power noise cannot be fully produced. Moreover,portions in which a decoupling capacity is to be inserted are decreasedwith an increase in the integration of the semiconductor device. Thus,there is a problem in that a sufficient decoupling capacity cannot beobtained.

Furthermore, it is necessary to take a pattern direction and a wiringdirection into consideration in the addition of a capacity. In aconventional pattern generating method, consequently, automation is hardto perform.

Therefore, it has been demanded that a bypass capacitor having a largercapacity is formed without an increase in an occupied area in order toreduce a power noise more reliably.

In the method, moreover, the operating frequency is not taken intoconsideration. In a semiconductor device to be driven at a specificoperating frequency, the effect of reducing a power noise cannot besufficiently obtained.

Thus, the use of the bypass capacitor comprising polysiliconconstituting a gate electrode, a bypass capacitor diffusion provided totake the shape of a ring on the outside of the polysilicon, and a bypasscapacitor contact provided on the polysilicon cannot take acountermeasure for absorbing a power noise for each frequencycharacteristic.

Although a capacitor having a large capacity may be provided in an ESDand a wiring between blocks and a capacitor having a small capacity maybe provided between the blocks in the same chip, moreover, the samenoise countermeasure is entirely taken and is not always effective.

The invention has been made in consideration of the actual circumstancesand has an object to effectively absorb a power noise and to implementthe stable operation of a circuit.

It is another object of the invention to easily automate patterngeneration in order to reliably reduce a power noise.

It is yet another object of the invention to form a capacitor having alarger capacity without increasing an occupied area in order to reduce apower noise more reliably.

It is a further object of the invention to implement the stableoperation of a circuit by properly using a capacity to absorb a powernoise depending on an operating frequency characteristic.

DISCLOSURE OF THE INVENTION

In order to attain the object, a semiconductor device according to theinvention serves to search for an empty region on a layout pattern,increase a bypass capacitor capacity by forming a capacitor in the emptyregion, change the shape of a bypass capacitor, insert an inductancecell and properly use the bypass capacitor depending on an operatingfrequency characteristic.

More specifically, the invention provides a semiconductor devicecomprising a bypass capacitor including an MOS structure having a gateelectrode formed to be extended from a power wiring region to a portionprovided under an empty region which is adjacent to the power wiringregion and has no other functional layer, and formed through acapacitive insulating film on a diffusion region having one conductivitytype, and a substrate contact formed under a ground wiring region andfixing a substrate potential, wherein the bypass capacitor has a contactto come in contact with the power wiring which is formed on a surface ofthe gate electrode and includes the diffusion region having the oneconductivity type and a diffusion region of the substrate contactconnected to each other.

According to such a structure, a diffusion region is formed to beextended under the empty region. Consequently, it is possible to formthe capacitor by utilizing the empty region without increasing a chiparea with a simple structure. Thus, a noise can be reduced. In thegeneration of a pattern, the layout pattern of a chip is generated andan adjacent empty region to a region in which a decoupling capacity canbe generated under the power wiring (a place in which other layers arenot present at all) is then searched automatically by utilizing agraphic logical operation and a resize processing, and the region thussearched is utilized as a decoupling capacity arrangement region. Thus,a pattern can be generated automatically and a noise can be reduced withhigh precision.

Moreover, a wiring layer to be a connecting destination can also beformed as a pattern. Thus, a noise can be reduced with higher precision.At this time, it is necessary to carry out the arrangement to observe adesign rule. Consequently, it is possible to form a reliable patternwith higher precision.

More specifically, all regions opposed to a diffusion region and a gateelectrode formed thereon act as a capacitor so that an area can beutilized very effectively. Moreover, an electric potential on thesubstrate side is also fetched through the diffusion region. Therefore,the pattern can be integrally formed over a large area because of a lowresistance for fetching an electric potential.

According to such a structure, moreover, a capacitor having a largecapacity can be connected between the power wiring and the ground wiringthrough a diffusion layer having a low resistance.

Accordingly, it is possible to provide a semiconductor device having agreat function of reducing an electromagnetic interference noise by ahigh-frequency operation. Furthermore, if a contact is independentlyformed on a gate electrode to change the electric potentials of the gateelectrode and the power wiring provided thereon, furthermore, it is alsopossible to form a capacity between the gate electrode and the powerwiring. Thus, a capacitor having a two-layer structure can be formed sothat a capacity can be increased.

It is desirable that the bypass capacitor should be constituted by aplurality of unit cells and the unit cells are arranged in a matrix inthe empty region.

According to such a structure, the units are arranged. Consequently, itis possible to easily carry out an operation and to readily form apattern at a high speed.

It is desirable that the diffusion region having the one conductivitytype should have the same conductivity type as that of the diffusionregion of the substrate contact.

According to such a structure, a connection to the substrate contact caneasily be carried out and a connecting resistance can be reduced.

It is desirable that the diffusion region having the one conductivitytype should be different from a conductivity type of the diffusionregion of the substrate contact, and the substrate contact and thediffusion region having the first conductivity type should be connectedto each other through a silicide layer formed on a surface of thediffusion region of the substrate contact.

According to such a structure, there is a problem in that a regionhaving a small number of carriers is formed on an interface because of areverse conductivity type and a connecting resistance is thus increasedif the connection is to be carried out at the diffusion layer in theconnecting portion to the substrate contact. By siliciding, thediffusion region provided under the gate electrode is connected throughthe silicide layer provided on the surface of the diffusion region.Consequently, the connecting resistance can be improved so that anexcellent bypass capacitor can be obtained.

Moreover, there is a problem in that a region having a small number ofcarriers is formed on an interface and the connecting resistance is thusincreased because of a reverse conductivity type if the connection is tobe carried out at the diffusion layer in the connecting portion to thesubstrate contact. By siliciding, the diffusion region provided underthe gate electrode is connected through the silicide layer provided onthe surface of the diffusion region. Consequently, the connectingresistance can be improved so that an excellent bypass capacitor can beobtained.

It is desirable that the diffusion region of the substrate contactshould be constituted by a first diffusion region to be an extendedregion of a diffusion region having the same conductivity type as thatof the diffusion region having the one conductivity type and a seconddiffusion region having a different conductivity type from that of thediffusion region having the one conductivity type, and the first andsecond diffusion regions should be connected to a ground wiring throughthe substrate contact and constitute a decoupling capacity having an MOStransistor structure, respectively.

According to such a structure, the capacitor having the MOS transistorstructure can be formed so that the capacity can be increased. Actually,a region in which the decoupling capacity can be arranged is extractedin the pattern generation, and the overlapping portion of the substratecontact region and the connecting diffusion layer is separated to carryout a connection to the wiring when the connecting diffusion layer is tobe provided. These steps can automatically be carried out by a graphiclogical operation and a resize processing.

When the decoupling capacity is to be actually used, there is no problemin a low frequency region of 10 to 100 Hz in an MOS diode structure. Ina high frequency band, an electric charge is taken in/out on thesubstrate terminal side of a depletion layer. Consequently, there is aproblem in that a capacity is reduced. By forming the decouplingcapacity having the MOS transistor structure, therefore, it is possibleto obtain a capacity which is approximately five times as much as thatin the conventional art.

It is desirable that the bypass capacitor should include a capacitorregion having a diffusion region having one conductivity type and asquare gate electrode formed integrally with a surface of the diffusionregion having the one conductivity type through a capacitive insulatingfilm, and a diffusion region to surround an outer periphery of thecapacitor region, and a diffusion region of a substrate contact shouldbe connected through the diffusion region and a power wiring to be anupper layer should be connected to a surface of the gate electrodethrough a plurality of contacts.

According to such a structure, in addition to the advantages, there isprovided the diffusion region on the outer periphery of the capacityregion. Consequently, it is possible to connect a connecting diffusionregion in every direction irrespective of a direction in which a powerwiring is extended. Consequently, the degree of freedom of a layout canalso be increased. Furthermore, a square shape is taken. Therefore, anarray can freely be obtained. In case of a multi-array, the arrangementcan be carried out efficiently and the degree of freedom of the arraycan also be increased.

The invention provides a semiconductor device comprising a first bypasscapacitor including an MOS structure formed under a power wiring regionand having a first gate electrode formed on a first diffusion regionhaving a first conductivity type through a capacitive insulating film soas to be connected to a power wiring, the first gate electrode beingconnected to a necessary diffusion potential for forming a transistorcapacity of the bypass capacitor on the ground wiring side, and a secondbypass capacitor including an MOS structure formed under a ground wiringregion and having a second gate electrode formed on a second diffusionregion having a different conductivity type from that of the firstdiffusion region through a capacitive insulating film so as to beconnected to a ground wiring, the second gate electrode being connectedto a necessary diffusion potential for forming a transistor capacity ofthe bypass capacitor on the power wiring side.

According to such a structure, the bypass capacitor to be a capacitiveelement is constituted on both the power supply side and the groundside. Consequently, a bypass capacitor having a large capacity can beobtained in a very small area.

It is desirable that the power wiring should be extended toward theground wiring side at an edge on the ground wiring side and should beconnected to the second diffusion region, and the ground wiring shouldbe extended toward the power wiring side at an edge on the power wiringside and should be connected to the first diffusion region.

According to such a structure, the connection can be achieved by only achange in a wiring pattern. Thus, manufacture can easily be carried out.

It is desirable that the power wiring and the ground wiring should bemutually protruded to take a shape of a comb-tooth on a boundarythereof.

According to such a structure, in addition to the advantages, a patternhaving a close packed structure can be formed.

It is desirable that the first and second diffusion regions should bemutually protruded to take a shape of a comb-tooth on a boundary betweenthe power wiring side and the ground wiring side.

According to such a structure, in addition to the advantages, a regionto be a connecting space is eliminated and a direct connection can becarried out. Consequently, an area efficiency can be enhancedconsiderably.

It is desirable that the first gate electrode of the first bypasscapacitor should have a wiring extended from the ground wiring side tothe power wiring side at an edge on the ground wiring side and should beconnected to the second diffusion region, and the second gate electrodeof the second bypass capacitor should have a wiring extended from thepower wiring side to the ground wiring side at an edge on the powerwiring side and should be connected to the first diffusion region.

It is desirable that the first and second gate electrodes should bemutually protruded to take a shape of a comb-tooth on a boundary betweenthe power wiring side and the ground wiring side.

According to such a structure, it is sufficient that the pattern of thegate electrode should be only changed, and the formation can easily becarried out. By causing a gate electrode structure on the lower layerside to be more complicated than the power wiring or the ground wiring,moreover, it is also possible to improve precision in a pattern, easilyform a pattern and enhance a yield.

It is desirable that at least one of the first bypass capacitor and thesecond bypass capacitor should have the first or second gate electrodeprovided with an opening portion for forming a contact region, and acontact of the first or second diffusion region should be formed throughthe opening portion.

According to such a structure, the gate electrode is formed to bedoughnut-shaped and the contact reaching the diffusion region is formedon a hole in a central part. Consequently, the degree of freedom isincreased in a connecting direction so that the degree of freedom of apattern layout can be increased.

It is desirable that a connection of the first gate electrode and thesecond diffusion region and a connection of the second gate electrodeand the first diffusion region should be carried out through a jointcell unit.

According to such a structure, the connection can be achieved withoutchanging the bypass capacitor region by using the joint cell unit.Consequently, the degree of freedom can be increased in a connectingdirection and the degree of freedom of a pattern layout can beincreased.

In addition, the pattern can easily be arranged automatically.

Moreover, the invention is characterized in that the bypass capacitorcomprises a capacitor region including a diffusion region having oneconductivity type and a gate electrode formed on a surface of thediffusion region having the one conductivity type through a capacitiveinsulating film and having an opening portion for forming a contactregion, and a diffusion contact to come in contact with the diffusionregion through the opening portion, and the gate electrode and thediffusion region are connected to have different electric potentials.

According to such a structure, the opening portion for forming a contactregion is provided on the gate electrode. By coming in contact with thediffusion region through the opening portion, the gate electrode and thediffusion region can be connected to have different electric potentials.For example, the formation can be carried out in any of adjacent regionsto the power wiring and the ground wiring. Thus, the decoupling capacitycan be added by utilizing an empty region.

It is desirable that the bypass capacitor should be generated in aminimum graphic dimension of a wiring pattern rule for manufacturing asemiconductor.

According to such a structure, a pattern design can automatically becarried out.

It is desirable that a plurality of bypass capacitors should be presentin an array under the power wiring.

According to such a structure, a capacitor having a large capacity canbe formed more efficiently.

Moreover, it is desirable that the bypass capacitor should comprisecapacitive insulating films which are different from each other andshould be formed in such a manner that a capacity per unit area isvaried in a chip.

In consideration of the specifications, the situation of the region isdecided from a design rule and bypass capacitors having differentcharacteristics are projected to be provided for each region. Ingeneral, a high breakdown voltage is required for a countermeasureagainst a surge in the outer peripheral portion of a chip which is closeto a power supply, while the high breakdown voltage is not particularlyrequired in an inner part. For this reason, the thickness of a gateinsulating film is increased in the vicinity of the outer periphery ofthe chip and is reduced in the inner part. Alternatively, it isnecessary to employ a method in which a gate insulating film having amultilayer structure is formed in only the vicinity of the outerperiphery of the chip in some cases.

Moreover, a frequency characteristic is important in the vicinity of afunctional element. While a bypass capacitor having a large capacity isto be formed for a high frequency, a bypass capacitor having a smallcapacity is enough for a low frequency.

Therefore, it is also possible to set a distance in an inner directionfrom a chip frame based on process information and to cut and divide anouter peripheral portion and an inner part by a logical operation and aresize processing, thereby arranging bypass capacitors having differentspecifications from each other. In consideration of the specifications,thus, the situation of a region is decided from the design rule toprovide bypass capacitors having different characteristics for theregions. Consequently, it is possible to provide a semiconductor devicehaving a more excellent characteristic and a high reliability.

Furthermore, the invention provides a semiconductor device comprising acapacitor region including a diffusion region having one conductivitytype and a gate electrode formed on a surface of the diffusion regionhaving the one conductivity type through a capacitive insulating filmand having an opening portion for forming a contact region, thediffusion region being connected to have a different electric potentialfrom that of the gate electrode through a diffusion contact to come incontact with the diffusion region through the opening portion.

According to such a structure, a contact is made with the diffusionregion of the substrate through the opening portion provided on the gateelectrode. Therefore, the structure can be applied in every wiringdirection. Thus, the degree of freedom of a wiring can be increased anda layout can be obtained very easily.

Moreover, the invention provides a semiconductor device comprising afirst pattern including a first rod pattern constituted by a lowerwiring formed on a surface of the semiconductor device and having firstand second lower pads on both ends, and third and fourth upper padsformed in opposite positions to each other through an interlayerinsulating film on the first and second lower pads, connected to thefirst and second lower pads through a contact hole and constituted by anupper wiring in such a manner that each pad is positioned in an almostsquare corner portion, a second pattern including a second rod patternconstituted by an upper wiring formed on the lower wiring through aninterlayer insulating film, having third and fourth upper pads on bothends and formed opposite in an orthogonal direction to the first rodpattern, and first and second lower pads formed in opposite positions toeach other through an interlayer insulating film on the third and fourthupper pads, connected to the third and fourth upper pads through acontact hole and constituted by a lower wiring in such a manner thateach pad is positioned in an almost square corner portion, and acapacitor unit pattern constituted to connect one of the pads of each ofthe first and second patterns to have a different electric potential.

According to such a structure, when the exact arrangement is carried outwithout depending on the vertical and transverse directions of a powerwiring, a capacitor can be formed well even if a connection is carriedout in any direction. Thus, the degree of freedom can be obtained over alayout and a semiconductor device capable of easily forming a patterncan be obtained. By utilizing an upper wiring and a lower wiring,moreover, a capacity can be formed three-dimensionally, that is, in avertical direction, a transverse direction and an oblique direction.Thus, it is possible to obtain a large decoupling capacity in a verysmall area.

It is desirable that the first and second rod patterns should havealmost the same widths and lengths, and the first pattern and the secondpattern should be constituted to almost overlap with each other.

According to such a structure, all overlapping regions in the verticaldirection, the transverse direction and the oblique direction becomecapacities. By utilizing the very small area at a maximum, therefore, itis possible to obtain a large decoupling capacity.

Moreover, it is desirable that edges of the pads for layers which arepositioned so as not to vertically overlap with each other should beprotruded from sides of the square and constitute a connecting region,and a shift region between the patterns should be formed pointsymmetrically in such a manner that only one connecting region isprotruded from each of the first pattern and the second pattern on eachof the sides.

According to such a structure, only a connecting region is exactlysuperposed on the wiring pattern. Consequently, the layout can easily becarried out and a reliability can be enhanced.

Furthermore, it is desirable that at least one of the sides of thesquare should be formed along an edge of a metal wiring and should beelectrically connected to the metal wiring through one of the pads.

According to such a structure, only the connecting region is exactlysuperposed on the wiring pattern of the metal wiring. Consequently, thelayout can easily be carried out and a reliability can be enhanced.

It is desirable that at least one of the sides of the square should beformed along an edge of a metal wiring and capacitor unit patterns inplural lines should be provided in such a manner that the side iselectrically connected to the metal wiring through one of the pads.

According to such a structure, the capacitor unit patterns in plurallines are provided. Therefore, a necessary capacity can be addedefficiently. Moreover, the degree of freedom of a layout can beincreased and a semiconductor device having a high reliability caneasily be obtained.

The invention provides a method comprising a layout pattern forming stepof designing and arranging a layout pattern of a semiconductor chip, anempty region detecting step of detecting an empty region in which thelayout pattern is not present, a wiring adjacent region detecting stepof detecting an adjacent region to a wiring region, a logical operationstep of carrying out a logical operation over a region detected at theempty region detecting step and a wiring region detected at the wiringadjacent region detecting step, and a capacity arranging step of settinga region extracted at the logical operation step to be a decouplingcapacity additional arrangement region, wherein a decoupling capacity isadditionally arranged in the empty region.

According to such a method, the empty region is detected and the bypasscapacitor is additionally provided in the empty region. Therefore,automatic formation can easily be carried out and a pattern layout canreadily be performed efficiently.

It is desirable that the capacity arranging step should include a bypasscapacitor frame generating step of arranging a bypass capacitor frame ona whole surface of a chip in order to automatically provide a formationpattern of a bypass capacitor to be a decoupling capacity, a bypasscapacitor arranging logical operation step of calculating a logicalproduct of a region provided under a power wiring of the layout patternand a decoupling capacity additional arrangement region and the bypasscapacitor frame, a bypass capacitor arrangement resizing step ofcarrying out scale-down/up over operation data on the logical product ofthe region provided under the power wiring and decoupling capacityadditional arrangement region and the bypass capacitor frame, therebycausing a very small pattern to disappear, and a connecting diffusionlayer logical operation step and a connecting diffusion layer resizingstep of generating a diffusion to connect the bypass capacitor regiondiffusion of the region provided under the power wiring and thedecoupling capacity additional arrangement region and a substratecontact region diffusion under a ground wiring.

According to such a structure, the pattern of the power wiring hasalready been generated prior to the generation of the pattern of thebypass capacitor. Consequently, it is possible to automatically generatethe pattern of the bypass capacitor included in the pattern of the powerwiring. More specifically, a semiconductor device having a highintegration and a small power noise can be formed based on a patternprovided automatically.

It is desirable that the bypass capacitor arrangement resizing stepshould serve to provide a bypass capacitor and to increase or reduce anumeric value of a half of an interval between the bypass capacitors toregulate data for forming a gate electrode, thereby increasing anddecreasing a capacitance value.

According to such a structure, pattern data can easily be obtainedefficiently. As data for forming a gate electrode, for example,polysilicon data, metal electrode data or metal silicide data are used.

It is desirable that a method of manufacturing a semiconductor deviceusing the method of generating the pattern of a semiconductor deviceshould further comprise a step of forming a semiconductor device and abypass capacitor based on the formation pattern of a bypass capacitorthus obtained.

According to such a structure, it is possible to automatically form asemiconductor device.

Moreover, the invention provides an apparatus for generating a patternfor a semiconductor device, comprising layout pattern forming means fordesigning and arranging a layout pattern of a semiconductor chip, emptyregion detecting means for detecting an empty region in which the layoutpattern is not present, wiring adjacent region detecting means fordetecting an adjacent region to a wiring region, logical operation meansfor carrying out a logical operation over a region detected by the emptyregion detecting means and a wiring region detected by the wiringadjacent region detecting means, and capacity arranging means forsetting a region extracted by the logical operation means to be adecoupling capacity additional arrangement region, wherein a decouplingcapacity is additionally arranged in the empty region.

According to such a structure, it is possible to automatically form asemiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a pattern generating apparatusaccording to a first embodiment of the invention.

FIG. 2 is a flowchart showing the details of a bypass capacitor patterngenerating procedure according to the first embodiment of the inventiontogether.

FIG. 3 is a plan view showing the chip of a semiconductor deviceaccording to the first embodiment of the invention and is a plan view inwhich a bypass capacitor frame is generated over the whole surface ofthe chip.

FIG. 4 is a plan view showing a graphic pattern in which an obstacle isremoved from a power wiring and a bypass capacitor frame.

FIG. 5 is a plan view in which the bypass capacitor frame is used togenerate a bypass capacitor.

FIG. 6 is a view in which an MOS transistor having a different polarityfrom the polarity of a substrate is automatically provided as a bypasscapacitor under a power wiring according to the first embodiment of theinvention.

FIG. 7 is a view in which an MOS transistor having the same polarity asthe polarity of the substrate is automatically provided as a bypasscapacitor under a power wiring according to a second embodiment of theinvention.

FIG. 8 is a view in which an MOS transistor according to a thirdembodiment of the invention is automatically provided as a bypasscapacitor.

FIG. 9 is an explanatory chart showing the advantage of the thirdembodiment of the invention.

FIG. 10 is a view showing a fourth embodiment of the invention.

FIG. 11 is a view showing a fifth embodiment of the invention.

FIG. 12 is a view showing a sixth embodiment of the invention.

FIG. 13 is a diagram showing a seventh embodiment of the invention.

FIG. 14 is a view showing the seventh embodiment of the invention.

FIG. 15 is a view showing the seventh embodiment of the invention.

FIG. 16 is a view showing the seventh embodiment of the invention.

FIG. 17 is a view showing the seventh embodiment of the invention.

FIG. 18 is a view showing an eighth embodiment of the invention.

FIG. 19 is a view showing a ninth embodiment of the invention.

FIG. 20 is a view showing an example of a bypass capacitor according toa conventional example.

In the drawings, 101 denotes layout pattern forming means, 102 denotesempty region detecting means, 103 denotes wiring adjacent regiondetecting means, 104 denotes logical operation means, and 105 denotescapacity arranging means.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the invention will be described below in detail withreference to the drawings.

FIRST EMBODIMENT

FIG. 1 is a block diagram showing a pattern generating apparatusaccording to an embodiment of the invention. The apparatus compriseslayout pattern forming means 101 for designing and arranging the layoutpattern of a semiconductor chip, empty region detecting means 102 fordetecting an empty region in which the layout pattern is not present onthe semiconductor chip, wiring adjacent region detecting means 103 fordetecting an adjacent region to a wiring region from the layout patternformed by the layout pattern forming means, logical operation means 104for carrying out a logical operation over a region detected by the emptyregion detecting means and a wiring region detected by the wiringadjacent region detecting means, and capacity arranging means 105 forsetting a region extracted by the logical operation means to be adecoupling capacity additional arrangement region, and has such astructure that a decoupling capacity is additionally provided in theempty region and layout pattern data subjected to a capacity additionagain are output from the layout pattern forming means 101.

More specifically, the pattern generating apparatus forms a layoutpattern subjected to the capacity addition as shown in FIG. 2. First ofall, the layout pattern of a semiconductor device comprising a bypasscapacitor pattern having an MIS structure constituted by a semiconductorsubstrate, a capacitive insulating film and an electrode is generatedfrom layout data 201 of the semiconductor device. Furthermore, an emptyregion in which the layout pattern is not present on a semiconductorchip is detected from the layout data (Step 202). Then, an adjacentregion to a wiring region is detected from a layout pattern formed bythe layout pattern forming means (Step 203). Moreover, the regiondetected by the empty region detecting means and the wiring regiondetected by the wiring adjacent region detecting means are subjected toa logical operation (Step 204) and a decoupling capacity additionalarrangement region is obtained (Step 205).

From data of a semiconductor device having the decoupling capacityadditional arrangement region thus obtained and provided with asubstrate contact under a ground wiring, a diffusion layer frame forminga bypass capacitor is provided based on a design rule 207 at a graphicpattern generating step 206, and furthermore, a semiconductor pattern isformed according to a technology calculated based on the design rule tocarry out a logical operation and a resize processing so that the layoutdata of a semiconductor device in which a bypass capacitor is presentunder a power wiring and in an additional region and a substrate contactis present under a ground wiring, and they are connected through adiffusion are obtained (209).

At the graphic pattern generating step 206, as will be described below,a bypass capacitor frame is formed based on a design rule 1004 fromlayout data 1001 of a semiconductor device in which a substrate contactis present under a power wiring and in an additional arrangement regionand a logical operation and a resizing step for arranging a bypasscapacitor are executed according to a technology 1005 calculated basedon the design rule, and furthermore, the layout data of thesemiconductor device having a bypass capacitor provided additionallyunder the power wiring are generated, and a logical operation andresizing for a connecting diffusion layer are carried out so that layoutdata 1003 of the semiconductor device in which the bypass capacitor andthe substrate contact are connected to each other through a diffusionlayer can be obtained automatically.

More specifically, at the graphic pattern generating step, the layoutdata 1005 of the semiconductor device in which the bypass capacitor isprovided under the power wiring and the substrate contact is providedunder the ground wiring are obtained through a bypass capacitor framegenerating step 1001 of automatically forming a bypass capacitor frameover a whole surface based on the design rule 207 from the layout dataof the semiconductor device in which the substrate contact is presentunder the ground wiring and in the additional arrangement region (theoutput data of the step 205), a bypass capacitor arranging logicaloperation step 1003 of carrying out a logical operation over thecovering bypass capacitor frame and a synthetic region (a syntheticregion of the ground wiring and the additional arrangement region), anda bypass capacitor arrangement resizing step 1004 of carrying out aresize to have an optimum size based on the technology 105 calculatedaccording to the design rule, and furthermore, there are provided aconnecting diffusion layer logical operation step 1006 of automaticallyarranging a connecting diffusion layer from the layout data and carryingout a logical operation and a connecting diffusion layer resizing step1007 of carrying out a resize to cause the connecting diffusion layer tohave an optimum size based on a technology 208 calculated according tothe design rule.

The technology calculated according to the design rule implies the sizeof a component such as a cell, a bypass capacitor or a wiring which isdefined by the design rule of each process such as a diffusion,sputtering or etching.

First of all, the layout pattern of the semiconductor device having thesubstrate contact under the ground wiring and in the additional region(the output of the Step 205) and the design rule 207 are input to thebypass capacitor frame generating step 1001 and the semiconductor device1002 covered with the bypass capacitor frame is output from the bypasscapacitor frame generating step 1001. At the bypass capacitor framegenerating step 1001, a chip size is measured and the number of arrayswhich can be provided therein is calculated in accordance with thedesign rule 207, and furthermore, the bypass capacitor frame in the samearray is provided on the semiconductor device having the substratecontact under the ground wiring and in the additional region so that thesemiconductor device covered with the bypass capacitor frame and havingthe substrate contact under the ground wiring and in the additionalregion is output.

Next, the semiconductor device covered with the bypass capacitor frameand having the substrate contact under the ground wiring and in theadditional region and the technology 208 calculated in accordance withthe design rule are input to the bypass capacitor arranging logicaloperation step 1003 and the bypass capacitor arrangement resizing step1004, and the layout data 1005 of the semiconductor device having thebypass capacitor under the power wiring and in the additional region andhaving the substrate contact under the ground wiring respectively areoutput from the bypass capacitor arranging logical operation step 1003and the bypass capacitor arrangement resizing step 1004. At the bypasscapacitor arranging logical operation step 1003 and the bypass capacitorarrangement resizing step 1004, a product of a region provided under thepower wiring and the additional region and a bypass capacitor array islogically calculated and the data are scaled down and up to cause a verysmall pattern to disappear. The bypass capacitor generation iscalculated in the same region in accordance with the technology 105obtained according to the design rule, and the semiconductor device 1005having the bypass capacitor under the power wiring and in the additionalregion and having the substrate contact under the ground wiringrespectively is output.

Subsequently, the semiconductor device 1005 having the bypass capacitorunder the power wiring and the substrate contact under the ground wiringand in the additional region and the technology 208 calculated inaccordance with the design rule are input to the connecting diffusionlayer logical operation step 1006 and the connecting diffusion layerresizing step 1007, and a semiconductor device having the bypasscapacitor under the power wiring and in the additional region and thesubstrate contact under the ground wiring respectively which areconnected through a diffusion is output from the connecting diffusionlayer logical operation step 1006 and the connecting diffusion layerresizing step 1007. At the connecting diffusion layer logical operationstep 1006 and the connecting diffusion layer resizing step 1007, thegeneration of a diffusion region for connecting a bypass capacitorregion diffusion under the power wiring and a substrate contact regiondiffusion under the ground wiring is calculated in accordance with thetechnology 208 obtained according to the design rule, and asemiconductor device having the bypass capacitor under the power wiringand the substrate contact under the ground wiring in which the bypasscapacitor and the ground wiring are connected to each other in thediffusion region is output. By using the layout pattern of thesemiconductor device, a semiconductor device is actually formed.

FIG. 3 is a plan view showing a part of an LSI chip at a graphic patterngenerating step according to the embodiment of the invention and a planview in which a bypass capacitor frame is generated over a wholesurface. The semiconductor device 1002 covered with the bypass capacitorfilm 9 and the technology 207 calculated in accordance with the designrule are input to the bypass capacitor arranging logical operation step1003 and the bypass capacitor arrangement resizing step 1004. A wiringcrossover through hole 2 for a line connection is removed from a powerwiring 1 of the semiconductor device 1002 covered with the bypasscapacitor frame at the bypass capacitor arranging logical operation step1003 so that a graphic pattern 3 in which an obstacle is removed fromthe power wiring and an additional arrangement region pattern 3 d aregenerated.

FIG. 4 is a plan view showing the execution of a logical operation of aproduct of a logical sum of the graphic pattern 3 in which the obstacleis removed from the power wiring in the previous item and the additionalarrangement region pattern 3 d and the bypass capacitor frame 9.

Furthermore, a half value of the minimum width of the bypass capacitorframe taking the logical expression of the product is defined into thetechnology 208 and a graphic pattern which becomes very small at thebypass capacitor arrangement resizing step 1004 by scale-down/up iserased.

FIG. 5 is a plan view in which the bypass capacitor frame 9 in theprevious item is used to generate a bypass capacitor. A half numericvalue of an interval between the bypass capacitor frames is defined intothe technology 208 from the bypass capacitor frame and diffusion data 11are generated by the execution of scale-up/down. A value correspondingto a certain numeric value is defined into the technology 208 from thebypass capacitor frame and polysilicon data 12 are generated by theexecution of the scale-down. The value of the certain numeric value isdefined into the technology 208 from the generated polysilicon and athrough hole 13 is generated by the execution of the scale-down.

Thus, there is formed a layout pattern of a semiconductor device shownin FIG. 6 which comprises a second bypass capacitor including a secondring-shaped polysilicon electrode 12 which is individually surrounded bya diffusion region 11, and a first bypass capacitor including a squaregate electrode 14 formed on an N⁺ diffusion layer 15 provided on thesurface of a substrate through a gate insulating film 14 g and a powerwiring 1 covering the gate electrode via a large number of through holes13 formed in an array. The first and second polysilicon electrodes 14and 12 are formed to be connected to the power wiring 1 via the throughhole 13 provided thereon respectively.

In the first bypass capacitor, thus, all regions opposed to the N⁺diffusion layer 15 extended to an empty region and the gate electrode 14formed thereon act as a capacitor and an area can be utilized veryeffectively.

Furthermore, a capacitor having a large area can also be formed betweenthe gate electrode 14 and the power wiring 1. Therefore, a capacitorhaving a two-layer structure can be formed so that a capacity can beincreased.

According to such a structure, moreover, a capacitor having a largecapacity can be connected through a diffusion layer having a lowresistance between a power wiring and a ground wiring. Accordingly, itis possible to provide a semiconductor device having a great function ofreducing an electromagnetic interference noise by a high-frequencyoperation.

With the structure of the first bypass capacitor, thus, a gate area canbe more increased than that in case of a gate electrode which takes theshape of a ring or a rectangle having a diffusion region on both sides.Consequently, a capacitor area can be increased considerably.

By using a new shape of a bypass capacitor in which the shape of anelectrode is changed, thus, a capacitance value can be more increasedthan that of the second bypass capacitor.

In the case in which a plurality of bypass capacitor frames are providedin a bypass capacitor region formed under the power wiring, a halfnumeric value of the interval between the polysilicons is defined intothe technology 208 and polysilicon data 14 are generated by theexecution of scale-up/down. Such a polysilicon shape causes a gate areato be further increased so that the capacitance value is increased.

FIGS. 6(a) to 6(c) are plan views (FIGS. 6(b) and 6(c) are A-A and B-Bsectional views of FIG. 6(a) respectively) in which a bypass capacitorhaving an MOS structure using a substrate contact under the groundwiring 5 and a diffusion region having a different conductivity typefrom that of a substrate under the power wiring 1 extended to anadditional formation region in a graphic pattern according to theembodiment of the invention is automatically arranged as a bypasscapacitor and the substrate contact provided under the ground wiring andthe bypass capacitor provided under the power wiring are connectedthrough a diffusion. The polarity of a diffusion region 15 for forming abypass capacitor is reverse to that of a diffusion 16 for the substratecontact. By forming a metal silicide layer 14S on the diffusion regionsurface 16 through a silicide process, however, it is possible toconnect the diffusion region 15 of the bypass capacitor to the diffusionregion 16 for the substrate contact with a low resistance. The bypasscapacitor frames are isolated from each other through an isolating film19 formed by an LOCOS method.

According to the embodiment, the bypass capacitor is automaticallyprovided under the power wiring 1. Consequently, it is possible toprovide a capacitance value for reducing a power noise withoutincreasing the area of a chip. Furthermore, the diffusion region 15 forbypass capacitor formation which is provided under the power wiring 5and the diffusion region 16 for substrate contact formation which isconstituted under the ground wiring are connected to each other.Consequently, the power wiring and the bypass capacitor, and the groundwiring 5 and the bypass capacitor can be connected to each other with alower resistance than that of the substrate having a high resistance.

The metal silicide layer 14S can also be formed at the same step as astep of siliciding other regions prior to the formation of a gateinsulating film. When a polysilicon layer constituting the gateelectrode of the bypass capacitor is to be silicided, moreover, the gateinsulating film is also patterned simultaneously with the patterning ofthe polysilicon and a metal layer is formed and silicided, and a portionwhich is not silicided, that is, the metal layer on the side surface ofthe gate insulating film is removed by selective etching. Consequently,a silicide layer can be formed on the surface of the substrate excludinga portion provided under the gate electrode. Also in this case, acurrent can be fetched without a PN junction and an excellent bypasscapacitor can be obtained.

SECOND EMBODIMENT

While the description has been given to the example in which the bypasscapacitor having the MOS structure using the diffusion region having areverse conductivity type to that of the substrate (P well) is formedunder the power wiring region extended to the empty region and isconnected through a salicide process, a bypass capacitor having an MOSstructure using a diffusion region having the same conductivity type asthat of a substrate (P well) is automatically arranged as a bypasscapacitor and a substrate contact provided under a ground wiring and thebypass capacitor provided under a power wiring are connected to eachother through a diffusion in this example.

More specifically, FIGS. 7(a) to 7(c) are plan views (FIGS. 7(b) and7(c) are A-A and B-B sectional views of FIG. 7(a) respectively) in whicha bypass capacitor having an MOS structure using a substrate contactunder a ground wiring and a diffusion region having the sameconductivity type as that of a substrate under a power wiring areautomatically arranged as a bypass capacitor in a graphic patternaccording to the embodiment of the invention, and the substrate contactprovided under the ground wiring and the bypass capacitor provided underthe power wiring are connected to each other through a diffusion.

According to the embodiment, the bypass capacitor is automaticallyarranged under the power wiring extended to an empty region so that acapacitance value for reducing a power noise can be provided withoutincreasing the area of a chip. Furthermore, a substrate contactformation diffusion 16 constituted under a ground wiring 5 is extendedand is connected to a bypass capacitor formation diffusion 15 providedunder a power wiring 1. Consequently, the power wiring and the bypasscapacitor, and the ground wiring 5 and the bypass capacitor can beconnected to each other with a lower resistance as compared with thesubstrate having a high resistance.

FIGS. 7(a) to 7(c) are plan views in which a bypass capacitor having anMOS structure using a substrate contact under the ground wiring 5 and adiffusion region having the same conductivity type as that of asubstrate under the power wiring 1 extended to an additional formationregion are automatically arranged as a bypass capacitor in a graphicpattern according to the embodiment of the invention, and the substratecontact provided under the ground wiring and the bypass capacitorprovided under the power wiring are connected to each other through adiffusion. A diffusion region 17 for bypass capacitor formation and adiffusion 16 for a substrate contact have the same polarity and areformed integrally with each other.

THIRD EMBODIMENT

While the description has been given to the example in which the bypasscapacitor having the MOS structure using the diffusion region having areverse conductivity type to that of the substrate (P well) is formedunder the power wiring region extended to the empty region and isconnected through the salicide process in the first embodiment, an N⁺type diffusion region 15 e (a diffusion region having a differentconductivity type from that of a substrate (P well)) extended for bypasscapacitor formation is further extended to a part of a substrate contactformation region and both a substrate contact 7 provided in contact witha contact diffusion region 16 under a ground wiring 5 and a connectingcontact 7 s provided in contact with the extended N⁺ type diffusionregion 15 e are connected to the ground wiring 5 in a substrate contactregion as shown in FIGS. 8(a) to 8(c) (FIGS. 8(b) and 8(c) are A-A andB-B sectional views of FIG. 8(a) respectively) in this example.

Other portions are formed in the same manner as those in the firstembodiment.

According to such a structure, a bypass capacitor having an MOStransistor structure is formed. The function of a capacity in an FMfrequency band is approximately five times as great as that of the MOSdiode structure, for example, the structure according to the firstembodiment, and it is possible to form a capacitor having a largercapacity in a very small area.

Actually, a region in which a decoupling capacity can be arranged isextracted in pattern generation and the overlapping portion of asubstrate contact region and a connecting diffusion layer is isolatedand a connection to a wiring is carried out when the connectingdiffusion layer is to be provided. These steps can be automaticallyexecuted by a graphic logical operation and a resize processing in thesame manner as in the first embodiment.

When the decoupling capacity is to be actually used, there is a problemin that a desirable capacity can be obtained in a low frequency regionof 10 to 100 Hz as shown in a capacity−voltage curve of a curve b and anelectric charge is taken in/out on the substrate terminal side of adepletion layer in a high frequency band so that a capacity is reducedas shown in a curve of a in a bypass capacitor having an MOS diodestructure as shown in an explanatory chart of FIG. 9. On the other hand,a decoupling capacity having an MOS transistor structure shown in FIG. 8is formed. Consequently, it is possible to obtain a capacity which isapproximately five times as large as that in the conventional art. Morespecifically, a depletion layer is expanded over a junction surface in anon-salicide structure. An electric charge is stored in the vicinity ofa channel at a low frequency. Therefore, a distance from the electriccharge stored in a gate terminal is small and a distance between thecapacity and the electric charge is inversely proportional. Therefore,the capacity can be maintained to be large. However, the electric chargespreads to the outside of the depletion layer at a high frequency and adistance from the electric charge of a gate capacity is increased sothat the capacity is reduced. The reason is that a long time is taken toform an inverted layer as a physical phenomenon so that the capacity canfollow a change in a voltage at a low frequency and cannot follow aquick change in a voltage at a high frequency. Thus, it is impossible toobtain the advantages of the capacity. By using the structure accordingto the invention, automatic generation can be carried out, and anelectric potential in the vicinity of a channel can be fixed and anelectric charge can be stored in the vicinity of the channel. Therefore,the capacity can be maintained to be large in a high frequency band.

FOURTH EMBODIMENT

In the third embodiment, the N⁺ type diffusion region 15 e (thediffusion region having a different conductivity type from that of asubstrate (P well)) extended for forming the bypass capacitor is furtherextended to a part of the substrate contact formation region under thepower wiring region extended to an empty region, and both the substratecontact 7 provided in contact with the contact diffusion region 16 underthe ground wiring 5 and the connecting contact 7 s provided in contactwith the extended N⁺ type diffusion region 15 e are connected to theground wiring 5 in the substrate contact region so that a bypasscapacitor cell is formed under the power wiring.

On the other hand, in this example, a bypass capacitor cell is formedunder both a power wiring and a ground wiring, a wiring is extended fromthe power wiring side to the ground wiring side and is connected to anecessary diffusion potential for forming a transistor capacity on thepower supply side, and furthermore, a wiring is extended from the groundwiring side to the power wiring side and is connected to a necessarydiffusion potential for forming a transistor capacity on the groundwiring side as shown in FIGS. 10(a) to 10(c) (FIGS. 10(b) and 10(c) areA-A and B-B sectional views of FIG. 10(a) respectively) in order togenerate a capacity in both the power wiring and the ground wiring.

For a layout, a contact region is provided like a comb-tooth. A wiringfor extension can be constituted by a metal wiring such as a gold wiringor a polysilicon wiring.

A region provided under a power wiring is formed in a p well 15 w and aregion provided under a ground wiring is formed in an n well 16 w.

The bypass capacitor cell on the power wiring side is constituted by ann⁺ diffusion layer 15 e formed in the p well 15 w and a gate electrode14 comprising a polysilicon layer formed through a gate insulating film14 g.

On the other hand, the bypass capacitor cell on the ground wiring sideis constituted by a p+ diffusion layer 16 formed in the n well 16 w andthe gate electrode 14 comprising the polysilicon layer formed throughthe gate insulating film 14 g.

In the bypass capacitor cell on the power wiring side, the p⁺ diffusionregion 16 formed in the n well 16 w on the ground wiring side and an n⁺diffusion region 16 c formed to penetrate through the n well 16 w in thep⁺ diffusion region 16 are connected to have the same potential throughcontacts 7 p and 7 n by the extension of an electrode wiring 1,respectively.

On the other hand, in the bypass capacitor cell on the ground wiringside, the n⁺ diffusion region 15 e formed in the p well 15 w on thepower wiring side and the p⁺ diffusion region 15 c formed to penetratethrough the p well 15 w in the n⁺ diffusion region 15 e are connected tohave the same potential through contacts 13 n and 13 p by the extensionof a ground wiring 5, respectively.

By such a structure, a capacitive element is constituted on the powersupply side and the ground side. Thus, it is possible to obtain a bypasscapacitor having a large capacity in a very small area.

FIFTH EMBODIMENT

In the fourth embodiment, the description has been given to thestructure in which the capacitive element is constituted on the powersupply side and the ground side and the bypass capacitor having a largecapacity is obtained in the very small area. While the p well 15 w andthe n well 16 w are formed under the power wiring and the ground wiringrespectively in the embodiment, a cell region actually becomes an emptyregion for a connection every line in the connection.

This example is characterized in that the p well 15 w and the n well 16w are alternately bulged like a comb-tooth to have a close packedstructure as shown in FIGS. 11(a) to 11(c) (FIGS. 11(b) and 11(c) areA-A and B-B sectional views of FIG. 11(a) respectively).

Consequently, a cell region required for the connection is reduced sothat a capacity can be increased.

The same portions have the same designations.

SIXTH EMBODIMENT

In the fourth embodiment, the description has been given to thestructure in which the capacitive element is constituted on the powersupply side and the ground side and the bypass capacitor having a largecapacity is obtained in the very small area. While the p well 15 w andthe n well 16 w are formed under the power wiring and the ground wiringrespectively in the embodiment, a cell region actually becomes an emptyregion for a connection every line in the connection.

This example is characterized in that an electric potential on thesubstrate potential side of the bypass capacitor is fetched through anopening portion 14 h formed in a gate electrode 14 as shown in FIG. 12in order to reduce the empty region.

More specifically, in this example, a bypass capacitor cell is formedunder both a power wiring and a ground wiring and the gate electrode ofeach bypass capacitor cell is extended from the power wiring side to theground wiring side and is connected to a power wiring 5 through acontact 5 g, and furthermore, is extended from the ground wiring side tothe power wiring side and is connected to the ground wiring 5 through acontact 1 g as shown in FIGS. 12(a) to 12(c) (FIGS. 12(b) and 12(c) areA-A and B-B sectional views of FIG. 12(a) respectively) in order togenerate a capacity in both the power wiring and the ground wiring.

For a layout, the gate electrode wiring 14 is extended like a comb-toothand is thus arranged.

In the same manner as in the embodiments, a region provided under thepower wiring is formed in the p well 15 w, and furthermore, a regionprovided under the ground wiring is formed in the n well 16 w.

The bypass capacitor cell on the power wiring side is constituted by ann⁺ diffusion layer 15 e formed in the p well 15 w and the gate electrode14 comprising a polysilicon layer formed through a gate insulating film14 g. In each bypass capacitor cell, the n⁺ diffusion layer 15 e can befetched through an opening portion 14 h formed on the gate electrode 14.

On the other hand, the bypass capacitor cell on the ground wiring sideis constituted by a p⁺ diffusion layer 16 formed in the n well 16 w andthe gate electrode 14 comprising a polysilicon layer formed through thegate insulating film 14 g. In each bypass capacitor cell, the p⁺diffusion layer 16 can be fetched through the opening portion 14 hformed on the gate electrode 14.

The gate electrode 14 of the bypass capacitor cell on the power wiringside connects the p⁺ diffusion region 16 formed in the n well 16 w onthe ground wiring side by the extension of the gate electrode 14 itselfto the ground wiring side and an n⁺ diffusion region 16 c formed topenetrate through the n well 16 w in the p⁺ diffusion region 16 throughcontacts 5 n and 5 p by the extension of an electrode wiring 1 via theopening portion 14 h formed on the gate electrode 14 from the groundwiring 5 to have the same electric potential, respectively.

On the other hand, the gate electrode 14 of the bypass capacitor cell onthe ground wiring side connects the n⁺ diffusion region 15 e formed inthe p well 15 w by the extension of the gate electrode itself to thepower wiring side and a p⁺ diffusion region 15 c formed to penetratethrough the p well 15 w in the n⁺ diffusion region 15 e through contacts1 n and 1 p via the opening portion 14 h formed on the gate electrode 14from the power wiring 1 to have the same electric potential,respectively. The connection is carried out to have the same electricpotential through contacts 13 n and 13 p by the extension of the groundwiring 5, respectively.

By such a structure, a capacitive element is constituted on the powersupply side and the ground side. Thus, it is possible to obtain a bypasscapacitor having a large capacity in a very small area.

In the embodiment, the opening portion for forming a contact region isprovided on the gate electrode and a contact is made with the diffusionregion through the opening portion so that the gate electrode and thediffusion region can be connected to have different electric potentials.For example, the formation can be carried out in any adjacent region towirings having different electric potentials such as a power wiring anda ground wiring. Thus, it is possible to add a decoupling capacity byutilizing an empty region.

SEVENTH EMBODIMENT

In the first to third embodiments, the description has been given to theexample in which the bypass capacitor is formed under the power wiringregion extended to the empty region. In the fourth to sixth embodiments,the description has been given to the example in which the bypasscapacitor is formed under the power wiring region and in the groundwiring region. In this example, as shown in FIG. 13, a verticalstructure pattern to be formed additionally is changed into a data baseand a layout inserting a decoupling capacity is formed from the database. More specifically, a decupling insertion layout 1314 is obtainedfrom layout information 1311 and a decoupling data base 1312 through adecoupling inductance capacity generating layer value 1313.

Various capacitor cell units are stored in the decoupling capacity database as shown in FIG. 14, for example, and can be utilized depending onnecessary conditions.

The capacitor cell unit is constituted by a first pattern A comprising afirst rod pattern 1403 a, constituted by a lower wiring formed on thesurface of a semiconductor device and having first and second lower pads1401 a and 1402 a on both ends and third and fourth upper pads 1404 aand 1405 a formed in opposite positions through an interlayer insulatingfilm (not shown) respectively, connected to the first and second lowerpads 1401 a and 1402 a through a contact hole h and constituted by anupper wiring to have each pad positioned in an almost square cornerportion, and a second pattern B comprising a second rod pattern 1403 bconstituted by an upper wiring formed on the lower wiring through aninterlayer insulating film, having third and fourth upper pads 1404 band 1405 b on both ends and formed opposite in an orthogonal directionto the first rod pattern and first and second lower pads 1401 b and 1402b formed in positions opposite to the third and fourth upper pads 1404 band 1405 b through an interlayer insulating film respectively, connectedto the third and fourth upper pads 1404 b and 1405 b through the contacthole h and constituted by a lower wiring having each pad positioned inan almost square corner portion, and one of the pads of each of thefirst and second patterns A and B is connected to have a differentelectric potential.

The first and second rod patterns A and B have almost the same widthsand lengths, and the first pattern and the second pattern areconstituted to almost overlap with each other. The edge of each of thepads positioned so as not to vertically overlap with each other for eachlayer on each side of a square is protruded from each side andconstitutes a connecting region. A shift region between the patterns isformed point symmetrically with each other in such a manner that onlyone connecting region is protruded from the first pattern and the secondpattern on each side, respectively.

With an increase in the integration of a semiconductor element, anaspect ratio is increased and the capacities of conductor layers in acontact hole are also increased as shown in an explanatory view of FIG.15.

According to such a structure, when the capacitor unit is exactlyarranged without depending on the vertical and transverse directions ofthe power wiring, a capacitor can be formed well even if a connection iscarried out in any direction. Thus, the degree of freedom can beacquired over a layout and a semiconductor device capable of easilyforming a pattern can be obtained. By utilizing an upper wiring and alower wiring, moreover, a capacity can be formed three-dimensionally,that is, in a vertical direction, a transverse direction and an obliquedirection. Thus, it is possible to obtain a large decoupling capacity ina very small area.

Furthermore, all overlapping regions in the vertical direction, thetransverse direction and the oblique direction become capacities. Byutilizing the very small area at a maximum, therefore, it is possible toobtain a large decoupling capacity.

Moreover, only a connecting region is exactly superposed on the wiringpattern. Consequently, the layout can easily be obtained and areliability can be enhanced.

Referring to the capacitor unit, as shown in FIG. 16, for example, apower supply or a metal wiring such as a ground wiring, and desirably,at least one of the sides of the square is formed along the edge of ametal wiring 1601 and is electrically connected to the metal wiring 1601through one of the pads. More specifically, the pads of one of first andsecond patterns 1602A and 1602B of a capacitor unit 1602 are alternatelyconnected and any of the pads is connected to a wiring having anotherelectric potential.

According to such a structure, only a connecting region is exactlysuperposed on the wiring pattern of the metal wiring. Consequently, alayout can easily be obtained and a capacity can readily be added byutilizing an empty region.

FIGS. 17(a) to 17(e) are views for explaining the pattern structure ofthe capacitor unit. As shown in FIG. 17(a), a first rod pattern 1403 ahaving first and second lower pads 1401 a and 1402 a and first andsecond lower pads 1401 b and 1402 b are formed on both ends in a firstlayer wiring (lower wiring). After an interlayer insulating film (notshown) is formed, a contact hole h is formed to come in contact witheach pad as shown in FIG. 17(b). Then, a second layer wiring (upperwiring) is formed and is subjected to patterning, thereby forming asecond rod pattern 1403 b having third and fourth upper pads 1404 b and1405 b and first and second upper pads 1404 a and 1405 a on both ends ina second layer wiring as shown in FIG. 17(c). FIG. 17(d) shows a statein which they are superposed and FIG. 17(e) is a sectional view.

EIGHTH EMBODIMENT

In the sixth embodiment, the description has been given to the examplein which the gate wirings are alternately extended and are thusconnected in the case in which the bypass capacitor is formed under thepower wiring region and in the ground wiring region. In this example,the deformed pattern of the capacitor unit (see FIG. 14) described inthe seventh embodiment is arranged in place of the extension of the gatewiring and is used as a joint cell 1602 as shown in FIGS. 18(a) to 18(c)(FIGS. 18(b) and 18(c) are A-A and B-B sectional views of FIG. 18(a)respectively). In FIG. 18(a), a metal layer is not shown.

According to such a structure, automation can easily be carried out witha simple structure and a capacity can also be formed in the joint cellitself comprising first patterns 1602A and 1602B. Consequently, it ispossible to form a capacitor having a large capacity in a very smallregion.

NINTH EMBODIMENT

A semiconductor device is characterized in that a bypass capacitorconstituting a decoupling capacity to be inserted corresponding to acircuit in a chip is divided into a bypass capacitor 1901 for a smallcapacity region and a bypass capacitor 1902 for a large capacity regionas shown in FIG. 19(a).

Each bypass capacitor comprises different capacitive insulating filmsfrom each other and is constituted in such a manner that a capacity perunit area is varied in a chip. FIG. 19(b) shows a semiconductor deviceprovided with a bypass capacitor having a constant capacity illustratedfor comparison.

In consideration of the specifications, the situation of the region isdecided from a design rule and bypass capacitors having differentcharacteristics are projected to be provided for respective regions. Ahigh breakdown voltage is required for a countermeasure against a surgein the outer peripheral portion of a chip which is close to a powersupply, while the high breakdown voltage is not particularly required inan inner part. For this reason, the thickness of a gate insulating filmis increased in the vicinity of the outer periphery of the chip and isreduced in the inner part.

Moreover, it is also possible to employ a method in which a gateinsulating film having a multilayer structure is formed in only thevicinity of the outer periphery of the chip.

Furthermore, a frequency characteristic is important in the vicinity ofa functional element. While a bypass capacitor having a large capacityis to be formed for a high frequency, a proper bypass capacitor isselected corresponding to a frequency band to be used in order to have asmall capacity for a low frequency.

In consideration of the specifications, thus, the situation of a regionis decided from the design rule to provide bypass capacitors havingdifferent characteristics for the respective regions. Consequently, itis possible to provide a semiconductor device having a more excellentcharacteristic and a higher reliability.

While the invention has been described in detail with reference to thespecific embodiments, it is apparent for the skilled in the art thatvarious changes and modifications can be made without departing from thespirit and scope of the invention.

The application is based on Japanese Patent Application (No.2001-356279) filed in Nov. 21, 2001 and the contents are quoted byreference.

Industrial Applicability

As described above, in the semiconductor device according to theinvention, a diffusion region is formed to be extended under the emptyregion. Consequently, it is possible to form the capacitor by utilizingthe empty region without increasing a chip area with a simple structure.Thus, a noise can be reduced. In the generation of a pattern, moreover,the layout pattern of a chip is generated and an adjacent empty regionto a region in which a decoupling capacity can be generated under thepower wiring (a place in which other layers are not present at all) isthen searched automatically by utilizing a graphic logical operation anda resize processing, and the region thus searched is utilized as adecoupling capacity arrangement region. Thus, a pattern can be generatedautomatically and a noise can be reduced with high precision.

Furthermore, a wiring layer to be a connecting destination can also beformed as a pattern. Thus, a noise can be reduced with higher precision.At this time, it is necessary to carry out the arrangement to observe adesign rule. Consequently, it is possible to form a reliable patternwith higher precision.

Moreover, the bypass capacitor is constituted by a plurality of unitcells and the unit cells are arranged in a matrix in the empty region.Thus, the units are arranged so that it is possible to easily carry outan operation and to readily form a pattern at a high speed in theautomatic formation.

It is desirable that the diffusion region having the one conductivitytype should have the same conductivity type as that of the diffusionregion of the substrate contact. Consequently, a connection to thesubstrate contact can easily be carried out and a connecting resistancecan be reduced.

It is desirable that the diffusion region having the one conductivitytype should have a different conductivity type from that of thediffusion region of the substrate contact, and the substrate contact andthe diffusion region having the first conductivity type should beconnected to each other through a silicide layer formed on a surface ofthe diffusion region of the substrate contact. Therefore, there is aproblem in that a region having a small number of carriers is formed onan interface because of a reverse conductivity type and a connectingresistance is thus increased if the connection is to be carried out atthe diffusion layer in the connecting portion to the substrate contact.By siliciding, the diffusion region provided under the gate electrode isconnected through the silicide layer provided on the surface of thediffusion region. Consequently, the connecting resistance can beimproved so that an excellent bypass capacitor can be obtained.

It is desirable that the diffusion region of the substrate contactshould be constituted by a first diffusion region to be an extendedregion of a diffusion region having the same conductivity type as thatof the diffusion region having the one conductivity type and a seconddiffusion region having a different conductivity type from that of thediffusion region having the one conductivity type, and the first andsecond diffusion regions should be connected to a ground wiring throughthe substrate contact and constitute a decoupling capacity having an MOStransistor structure. Consequently, the capacitor having the MOStransistor structure can be formed so that the capacity can beincreased.

It is desirable that the bypass capacitor should include a capacitorregion having a diffusion region having one conductivity type and asquare gate electrode formed integrally with a surface of the diffusionregion having the one conductivity type through a capacitive insulatingfilm, and a diffusion region to surround an outer periphery of thecapacitor region, and a diffusion region of a substrate contact shouldbe connected through the diffusion region and a power wiring to be anupper layer should be connected to a surface of the gate electrodethrough a plurality of contacts so that an MOS transistor structure isconstituted. In addition to the advantages, consequently, there isprovided the diffusion region on the outer periphery of the capacityregion. Therefore, it is possible to connect a connecting diffusionregion in every direction irrespective of a direction in which a powerwiring is extended. Consequently, the degree of freedom of a layout canalso be increased. Furthermore, a square shape is taken. Therefore, anarray can freely be obtained. In case of a multi-array, the arrangementcan be carried out efficiently and the degree of freedom of the arraycan also be increased.

Moreover, the invention provides a semiconductor device comprising afirst bypass capacitor including an MOS structure formed under a powerwiring region and having a gate electrode formed on a first diffusionregion having one conductivity type through a capacitive insulatingfilm, having a wiring extended from the power wiring side to the groundwiring side and connected to a necessary diffusion potential for forminga transistor capacity of the bypass capacitor on the ground wiring side,and a second bypass capacitor including an MOS structure formed under aground wiring region and having a gate electrode formed on a diffusionregion having a different conductivity type from that of the firstdiffusion region through a capacitive insulating film, having a wiringextended from the ground wiring side to the power wiring side andconnected to a necessary diffusion potential for forming a transistorcapacity of the bypass capacitor on the power wiring side. Consequently,a capacitive element is constituted on both the power supply side andthe ground side. Thus, it is possible to obtain a bypass capacitorhaving a large capacity in a very small area.

It is desirable that the opening portion for forming a contact regionshould be provided on the gate electrode of the bypass capacitor. Bycoming in contact with the diffusion region through the opening portion,the gate electrode and the diffusion region can be connected to havedifferent electric potentials. For example, the formation can be carriedout in any of adjacent regions to the power wiring and the groundwiring. Thus, the decoupling capacity can be added by utilizing an emptyregion.

It is desirable that the bypass capacitor should be generated in aminimum graphic dimension of a wiring pattern rule for manufacturing asemiconductor. Consequently, a pattern design can automatically becarried out.

It is desirable that a plurality of bypass capacitors should be presentin an array under the power wiring. Consequently, a capacitor having alarge capacity can be formed more efficiently.

Moreover, it is desirable that the bypass capacitor should comprisecapacitive insulating films which are different from each other andshould be formed in such a manner that a capacity per unit area isvaried in a chip. According to such a structure, in consideration of thespecifications, the situation of the region can be decided from a designrule and bypass capacitors having different characteristics forrespective regions can be provided.

Furthermore, the invention provides a semiconductor device comprising afirst pattern including a first rod pattern constituted by a lowerwiring formed on a surface of the semiconductor device and having firstand second lower pads on both ends, and third and fourth upper padsformed in opposite positions to each other through an interlayerinsulating film on the first and second lower pads, connected to thefirst and second lower pads through a contact hole and constituted by anupper wiring in such a manner that each pad is positioned in an almostsquare corner portion, a second pattern including a second rod patternconstituted by an upper wiring formed on the lower wiring through aninterlayer insulating film, having third and fourth upper pads on bothends and formed opposite in an orthogonal direction to the first rodpattern, and first and second lower pads formed in opposite positions toeach other through an interlayer insulating film on the third and fourthupper pads, connected to the third and fourth upper pads through acontact hole and constituted by a lower wiring in such a manner thateach pad is positioned in an almost square corner portion, and acapacitor unit pattern constituted to connect one of the pads of each ofthe first and second patterns to have a different electric potential. Byexact arrangement without depending on the vertical and transversedirections of the power wiring, consequently, a capacitor can be formedwell even if a connection is carried out in any direction. Thus, thedegree of freedom can be acquired over a layout and a semiconductordevice capable of easily forming a pattern can be obtained. By utilizingan upper wiring and a lower wiring, moreover, a capacity can be formedthree-dimensionally, that is, in a vertical direction, a transversedirection and an oblique direction. Thus, it is possible to obtain alarge decoupling capacity in a very small area.

It is desirable that the first and second rod patterns should havealmost the same widths and lengths, and the first pattern and the secondpattern should be constituted to almost overlap with each other.Consequently, all overlapping regions in the vertical direction, thetransverse direction and the oblique direction become capacities. Byutilizing the very small area at a maximum, therefore, it is possible toobtain a large decoupling capacity.

Moreover, it is desirable that edges of the pads for layers which arepositioned so as not to vertically overlap with each other should beprotruded from sides of the square and constitute a connecting region,and a shift region between the patterns should be formed pointsymmetrically in such a manner that only one connecting region isprotruded from each of the first pattern and the second pattern on eachof the sides. Consequently, only a connecting region is exactlysuperposed on the wiring pattern. Thus, the layout can easily be carriedout and a reliability can be enhanced.

Furthermore, it is desirable that at least one of the sides of thesquare should be formed along an edge of a metal wiring and should beelectrically connected to the metal wiring through one of the pads.Consequently, only the connecting region is exactly superposed on thewiring pattern of the metal wiring. Thus, the layout can easily beobtained and a reliability can be enhanced.

It is desirable that at least one of the sides of the square should beformed along an edge of a metal wiring and capacitor unit patterns inplural lines should be provided in such a manner that the side iselectrically connected to the metal wiring through one of the pads.Consequently, a necessary capacity can be added efficiently. Moreover,the degree of freedom of a layout can be increased and a semiconductordevice having a high reliability can easily be obtained.

In the method according to the invention, the empty region is detectedand the bypass capacitor is additionally provided in the empty region.Therefore, automatic formation can easily be carried out and a patternlayout can readily be obtained efficiently.

It is desirable that the pattern of the power wiring has already beengenerated prior to the generation of the pattern of the bypasscapacitor. Consequently, it is possible to automatically generate thepattern of the bypass capacitor included in the pattern of the powerwiring. More specifically, a semiconductor device having a highintegration and a small power noise can be formed based on a patternprovided automatically.

It is desirable that the bypass capacitor arrangement resizing stepshould serve to provide a bypass capacitor and to increase or reduce anumeric value of a half of an interval between the bypass capacitors toregulate data for forming a gate electrode, thereby increasing anddecreasing a capacitance value. Consequently, pattern data can easily beobtained efficiently. As data for forming a gate electrode, for example,polysilicon data, metal electrode data or metal silicide data are used.

As described above, according to the structure, it is possible toautomatically form the layout pattern of a semiconductor device capableof effectively executing the absorption of a power noise andimplementing the stable operation of a circuit.

1. A semiconductor device comprising a bypass capacitor including an MOSstructure having a gate electrode formed to be extended from a powerwiring region of the semiconductor device to a portion provided under anempty region which is adjacent to the power wiring region and has noother functional layer, and formed through a capacitive insulating filmon a diffusion region having one conductivity type; and a substratecontact formed under a ground wiring region and fixing a substratepotential, wherein the bypass capacitor has a contact to come in contactwith the power wiring which is formed on a surface of the gate electrodeand includes the diffusion region having the one conductivity type and adiffusion region of the substrate contact connected to each other. 2.The semiconductor device according to claim 1, wherein the bypasscapacitor is constituted by a plurality of unit cells and the unit cellsare arranged in a matrix in the empty region.
 3. The semiconductordevice according to claim 1 or 2, wherein the diffusion region havingthe one conductivity type has the same conductivity type as that of thediffusion region of the substrate contact.
 4. The semiconductor deviceaccording to any of claims 1 to 3, wherein the diffusion region havingthe one conductivity type has a different conductivity type from that ofthe diffusion region of the substrate contact, and the substrate contactand the diffusion region having the first conductivity type areconnected to each other through a silicide layer formed on a surface ofthe diffusion region of the substrate contact.
 5. The semiconductordevice according to claim 1, wherein the diffusion region of thesubstrate contact is constituted by a first diffusion region to be anextended region of a diffusion region having the same conductivity typeas that of the diffusion region having the one conductivity type and asecond diffusion region having a different conductivity type from thatof the diffusion region having the one conductivity type, and the firstand second diffusion regions are connected to a ground wiring throughthe substrate contact and constitute a decoupling capacity having an MOStransistor structure, respectively.
 6. The semiconductor deviceaccording to any of claims 1 to 5, wherein the bypass capacitor includesa capacitor region having a diffusion region having one conductivitytype and a square gate electrode formed integrally with a surface of thediffusion region having the one conductivity type through a capacitiveinsulating film, and a diffusion region to surround an outer peripheryof the capacitor region, and a diffusion region of a substrate contactis connected through the diffusion region and a power wiring to be anupper layer is connected to a surface of the gate electrode through aplurality of contacts.
 7. The semiconductor device according to any ofclaims 1 to 5, wherein the bypass capacitor comprises a capacitor regionincluding a diffusion region having one conductivity type and a gateelectrode formed on a surface of the diffusion region having the oneconductivity type through a capacitive insulating film and having anopening portion for forming a contact region, and a diffusion contact tocome in contact with the diffusion region through the opening portion,and the gate electrode and the diffusion region are connected to havedifferent electric potentials.
 8. The semiconductor device according toany of claims 1 to 7, wherein the bypass capacitor is generated in aminimum graphic dimension of a wiring pattern rule for manufacturing asemiconductor.
 9. The semiconductor device according to any of claims 1to 8, wherein a plurality of bypass capacitors are present in an arrayunder the power wiring.
 10. The semiconductor device according to any ofclaims 1 to 9, wherein the bypass capacitor comprises capacitiveinsulating films which are different from each other and is formed insuch a manner that a capacity per unit area is varied in a chip.
 11. Asemiconductor device comprising a first bypass capacitor including anMOS structure formed under a power wiring region of the semiconductordevice and having a first gate electrode formed on a first diffusionregion having a first conductivity type through a capacitive insulatingfilm so as to be connected to a power wiring, the first gate electrodebeing connected to a necessary diffusion potential for forming atransistor capacity of the bypass capacitor on the ground wiring side;and a second bypass capacitor including an MOS structure formed under aground wiring region and having a second gate electrode formed on asecond diffusion region having a different conductivity type from thatof the first diffusion region through a capacitive insulating film so asto be connected to a ground wiring, the second gate electrode beingconnected to a necessary diffusion potential for forming a transistorcapacity of the bypass capacitor on the power wiring side.
 12. Thesemiconductor device according to claim 11, wherein the power wiring isextended toward the ground wiring side at an edge on the ground wiringside and is connected to the second diffusion region, and the groundwiring is extended toward the power wiring side at an edge on the powerwiring side and is connected to the first diffusion region.
 13. Thesemiconductor device according to claim 12, wherein the power wiring andthe ground wiring are mutually protruded to take a shape of a comb-toothon a boundary thereof.
 14. The semiconductor device according to claim11, wherein the first and second diffusion regions are mutuallyprotruded to take a shape of a comb-tooth on a boundary between thepower wiring side and the ground wiring side.
 15. The semiconductordevice according to claim 11, wherein the first gate electrode of thefirst bypass capacitor has a wiring extended from the ground wiring sideto the power wiring side at an edge on the ground wiring side and isconnected to the second diffusion region, and the second gate electrodeof the second bypass capacitor has a wiring extended from the powerwiring side to the ground wiring side at an edge on the power wiringside and is connected to the first diffusion region.
 16. Thesemiconductor device according to claim 15, wherein the first and secondgate electrodes are mutually protruded to take a shape of a comb-toothon a boundary between the power wiring side and the ground wiring side.17. The semiconductor device according to any of claims 11 to 16,wherein at least one of the first bypass capacitor and the second bypasscapacitor has the first or second gate electrode provided with anopening portion for forming a contact region, and a contact of the firstor second diffusion region is formed through the opening portion. 18.The semiconductor device according to claim 11, wherein a connection ofthe first gate electrode and the second diffusion region and aconnection of the second gate electrode and the first diffusion regionare carried out through a joint cell unit.
 19. A semiconductor devicecomprising a capacitor region including a diffusion region having oneconductivity type and a gate electrode formed on a surface of thediffusion region having the one conductivity type through a capacitiveinsulating film and having an opening portion for forming a contactregion, the diffusion region being connected to have a differentelectric potential from that of the gate electrode through a diffusioncontact to come in contact with the diffusion region through the openingportion.
 20. A semiconductor device comprising a first pattern includinga first rod pattern constituted by a lower wiring formed on a surface ofthe semiconductor device and having first and second lower pads on bothends, and third and fourth upper pads formed in opposite positions toeach other through an interlayer insulating film on the first and secondlower pads, connected to the first and second lower pads through acontact hole and constituted by an upper wiring in such a manner thateach pad is positioned in an almost square corner portion; a secondpattern including a second rod pattern constituted by an upper wiringformed on the lower wiring through an interlayer insulating film, havingthird and fourth upper pads on both ends and formed opposite in anorthogonal direction to the first rod pattern, and first and secondlower pads formed in opposite positions to each other through aninterlayer insulating film on the third and fourth upper pads, connectedto the third and fourth upper pads through a contact hole and havingfirst and second lower pads constituted by a lower wiring in such amanner that each pad is positioned in an almost square corner portion;and a capacitor unit pattern constituted to connect one of the pads ofeach of the first and second patterns to have a different electricpotential.
 21. The semiconductor device according to claim 20, whereinthe first and second rod patterns have almost the same widths andlengths, and the first pattern and the second pattern are constituted toalmost overlap with each other.
 22. The semiconductor device accordingto claim 21, wherein edges of the pads for layers which are positionedso as not to vertically overlap with each other are protruded from sidesof the square and constitute a connecting region, and a shift regionbetween the patterns is formed point symmetrically in such a manner thatonly one connecting region is protruded from each of the first patternand the second pattern on each of the sides.
 23. The semiconductordevice according to claim 21 or 22, wherein at least one of the sides ofthe square is formed along an edge of a metal wiring and is electricallyconnected to the metal wiring through one of the pads.
 24. Thesemiconductor device according to any of claims 21 to 23, wherein atleast one of the sides of the square is formed along an edge of a metalwiring and capacitor unit patterns in plural lines are provided in sucha manner that the side is electrically connected to the metal wiringthrough one of the pads.
 25. A method of generating a pattern for asemiconductor device comprising: a layout pattern forming step ofdesigning and arranging a layout pattern of a semiconductor chip; anempty region detecting step of detecting an empty region in which thelayout pattern is not present; a wiring adjacent region detecting stepof detecting an adjacent region to a wiring region; a logical operationstep of carrying out a logical operation over a region detected at theempty region detecting step and a wiring region detected at the wiringadjacent region detecting step; and a capacity arranging step of settinga region extracted at the logical operation step to be a decouplingcapacity additional arrangement region, wherein a decoupling capacity isadditionally arranged in the empty region.
 26. The method of generatinga pattern for a semiconductor device according to claim 25, wherein thecapacity arranging step includes: a bypass capacitor frame generatingstep of arranging a bypass capacitor frame on a whole surface of a chipin order to automatically provide a formation pattern of a bypasscapacitor to be a decoupling capacity; a bypass capacitor arranginglogical operation step of calculating a logical product of a regionprovided under a power wiring of the layout pattern and a decouplingcapacity additional arrangement region and the bypass capacitor frame; abypass capacitor arrangement resizing step of carrying out scale-down/upover operation data on the logical product of the region provided underthe power wiring and decoupling capacity additional arrangement regionand the bypass capacitor frame, thereby causing a very small pattern todisappear; and a connecting diffusion layer logical operation step and aconnecting diffusion layer resizing step of generating a diffusion toconnect the bypass capacitor region diffusion of the region providedunder the power wiring and the decoupling capacity additionalarrangement region and a substrate contact region diffusion under aground wiring.
 27. The method of generating a pattern for asemiconductor device according to claim 26, wherein the bypass capacitorarrangement resizing step serves to provide a bypass capacitor and toincrease or reduce a numeric value of a half of an interval between thebypass capacitors to regulate data for forming a gate electrode, therebyincreasing and decreasing a capacitance value.
 28. A method ofmanufacturing a semiconductor device comprising a step of forming asemiconductor device based on the pattern for the semiconductor devicewhich is generated according to any of claims 25 to
 27. 29. An apparatusfor generating a pattern for a semiconductor device, comprising: layoutpattern forming means for designing and arranging a layout pattern of asemiconductor chip; empty region detecting means for detecting an emptyregion in which the layout pattern is not present; wiring adjacentregion detecting means for detecting an adjacent region to a wiringregion; logical operation means for carrying out a logical operationover a region detected by the empty region detecting means and a wiringregion detected by the wiring adjacent region detecting means; andcapacity arranging means for setting a region extracted by the logicaloperation means to be a decoupling capacity additional arrangementregion, wherein a decoupling capacity is additionally arranged in theempty region.